The present invention relates to a semiconductor integrated circuit device and, for example, to a technique which is effective for use in an amplification circuit, such as a main amplifier suitable for a semiconductor storage device which is required to perform a reading operation at high speed.
It was found by investigation subsequent to the present invention that there is known technology related to the present invention. For example, there are descriptions of such technology in Japanese Unexamined Patent Application Nos. 8(1996)-227581 (hereinbelow, called conventional art 1) and 6(1994)-349282 (corresponding to U.S. Pat. No. 5,1455,802, hereinbelow called conventional art 2). The publication of the conventional art 1 discloses that two latch-type sense amplifiers of different data latching timings are used; and, when outputs of the sense amplifiers are different from each other, priority is placed on the output of the sense amplifier whose latch timing is later. The publication of the conventional art 2 discloses that two dynamic sense amplifiers for reading data of memory cells at different timings are provided; and, when an output of the sense amplifier whose latch timing is later is different from an output that whose latch timing is earlier, priority is placed on the output of the sense amplifier whose latch timing is later. The publications of the conventional arts 1 and 2 do not describe the necessity of realizing higher processing speed at the time of continuous operation and provision of a simpler circuit, as achieved by the present invention.
The conventional arts 1 and 2 are directed to the prevention of erroneous operation due to process variations and fluctuations in power and do not consider improvement in practical memory operation speed. Specifically, in the case of operating two latch-type amplifiers at different timings, as described above, the time necessary for an amplifying operation of the two amplifiers certainly increases in accordance with the amount of deviation between the timings. A memory circuit mounted on a digital signal processing system, such as a microcomputer, is hardly accessed discretely. Unlike the conventional arts 1 and 2, therefore, it is not so important for a memory circuit used in digital signal processing to shorten the time from the start of access to a memory cell until the output of the data.
In a digital signal process, data is successively written/read to/from a memory circuit. In the case of successively reading plural storage data, after amplifying the data, it is necessary to reset the amplifying state of the amplification circuit and perform an operation for amplifying the next data. In order to perform such a successive data amplifying operation at high speed, it is important to shorten the operation period of the amplification circuit. When two latch circuits are provided as described above, other problems arise, in that the circuit scale enlarges accordingly and the power consumption increases.
An object of the invention is to provide a semiconductor integrated circuit device, including an amplification circuit, which is capable of realizing a higher practical processing speed and an improved operation margin.
Another object of the invention is to provide a semiconductor integrated circuit device, including an amplification circuit, which is capable of realizing higher processing speed and an improved operation margin, and, in addition, has a smaller area and exhibits a power saving.
The above and other objects and novel features of the invention will become apparent from the following description and the attached drawings.
An embodiment of the invention disclosed herein will be briefly described as follows. A selection circuit is provided for first and second latch circuits which operate in response to first and second operation timing signals, respectively. By use of the selection circuit, a first operation of transmitting a signal corresponding to a first output signal of the first latch circuit to a third output terminal, and a second operation of transmitting a second output signal in place of the first output signal to the third output terminal when the first output is different from the second output signal of the second latch circuit are performed. The second operation timing signal is generated after the first operation timing signal, and the operation period of the second latch circuit is shortened according to the operation frequency in the first operation.